FinFET and Planar MOSFET Layout and Model
The FinFET structure has been around for some time, but has only been introduced commercially in recent years. Most semiconductor foundries are introducing FinFETs as they build technologies below the 20nm process node. A FinFET offers many electrical advantages over traditional planar MOSFETs that I won't discuss here. With a FinFET, the channel is 'raised' into a fin, with the gate wrapped around it. From a 3-dimensional perspective, this is quite complex, but for mask manufacturing purposes, it requires a standard set of 2-D masks.The standard device model of a FinFET is a 3-terminal device with optional bulk nodes. The FinFET netlist topology is identical to that of the planar MOSFET. In addition to the length and width parameters, it will include additional device properties describing FIN configurations.
FinFETs and DRC
A DRC tool's job is to look at layers of 2-D geometries and report errors due to interactions and measurements:- on a single mask layer
- between multiple layers
- between layers in context of a complex net-connection structure (ie same-net checks, antenna checks, net-voltage checks)
If we consider this in context of a FinFET - you can see that a FinFET is built from a simple collection of 2-D masks. While it may have many additional rules - the rules will all fit into one of the 3 categories above. What we are finding in practice is that to effectively manufacture these devices at extremely tight pitches, the design rules for FinFET layers are much more restrictive, and in some ways, much simpler to manage as a designer than planar MOSFET rules.
FinFETs and LVS
An LVS tool's job is to extract and compare MOSFET devices (plus any other device types which are not relevant to this discussion). At a minimum, it must extract a MOSFET with gate, source, and drain terminals. For most modern technologies, the LVS tool must also extract at least one bulk terminal. Standard properties extracted and compared on MOSFETs are width and length.As you can see from the image above, the 2-D layout of a FinFET is nearly identical to a planar MOSFET. Therefore, the task of identifying and extracting the FinFET device is trivial for an LVS tool that can extract a 4-terminal MOSFET. Calculation of the FinFET properties requires slightly different measurement techniques than for a planar MOSFET. Fortunately, most modern LVS tools have had features to support this for many technology nodes.
Summary
DRC and LVS tools that support recent process nodes should have no difficulty supporting the additional demands of FinFETs. A foundry writing DRC and LVS runsets to support FinFETs will face additional complexities of adding new DRC rules, and supporting FinFET device definition/properties for LVS. As a designer, you may experience different types of rules, and different failure modes in LVS. However, the software itself should support FinFETs without modification.Keep in mind that I refer here only to the impact of FinFET - there are many other features of sub-20nm technologies that will impact Physical Verification tools that I will discuss in future blog posts.
I invite any feedback and comments.
