Simultaneous Multi-Chip 3D-IC Physical Verification

In my last post, I hinted that single chip 3D-IC physical verification was an incremental change to design.  Today I'll explore a disruptive change: verify the multiple chips in a single DRC and LVS run.  There are many practical reasons why this is not done (hard to merge libraries, division of design activities, foundry support, etc) - but many people have asked about it - so here are my thoughts on how it could be done.  Keep in mind - I am not aware of anyone making any serious attempts to do this.  If you are aware of any (or you want to try to do this), please post a comment or email me.

Why Do Simultaneous 3-D Design?

With traditional monolithic designs, system designers must make careful decisions about which circuits go on which chips, and expensive I/O circuits and off-chip interconnects must connect related functional circuits.  The promise of 3D-IC is to significantly reduce the cost of communication between chips.  Taking this to an extreme, the chip-abstractions could go away, and during system design, circuits could be moved fluidly between chips.  This is clearly an extreme, as even the small TSVs still have some cost, but it is now realistic to keep the clocks on the different chips synchronized so that connections between the chips can also be synchronous with internal clocks.

Merged 3D-IC Design Process

Let's create a theoretical chip design process.  I’m leaving a lot of questions unanswered, including placement, routing, and timing.  Perhaps I’ll circle back to providing some thoughts on that if there is enough interest.  From a physical verification perspective, we care about:

• Use interposer 3D-IC design style
• Common node for functional chips (20nm, 8 metal)
• Cheaper node for interposer (180nm, 3 layer metal)
• Single Verilog defines the entire system
• 20nm functional standard cell library (with SPICE)
• 180nm interposer buffer library (with SPICE)
• The individual chip layouts are merged to a single layout
• Using interposer origin
• Chip instance origins aligned to interposer
• Uniquified interposer mask layer numbers

Layout Merging

The chips layouts are instantiated against the interposer coordinate reference

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The layers from each chip type could be stored in a single layout file.

DRC

Because we have two processes (20nm and 180nm), we need start with two DRC decks, and we need to somehow 'merge' them.  However, its not as simple as concatenating them.  Because the layer numbers have changed for the Interposer, we need to update the layer assignments in the 180nm DRC runset.  There may be other considerations when merging the runsets as well.  For example, any 'density' checks on the functional chips need to be made aware that there are regions of the merged layout that are not part of the functional die (see image below).  Another consideration is layer naming in the runset.  Depending on how the runsets are written and syntax restrictions of the runset language, name collision is possible (for example, both technologies probably refer to first metal as "m1").  In that case, the layers will need to be renamed with some convention (ie prefixing).

LVS

Similar to the process described for DRC, the LVS can be merged.  The basic connections inside each chip can be unchanged, but we need to include the statements describing how the nets on the individual chips are interconnected.  Merging LVS runsets will be much more complicated than with DRC.  Since we desire 1 netlist as a result of the procedures executed by each runset, the 'netlisting' phase must be merged.  That means all of the extraction steps prior to netlist (connect + extract) need to be merged.  Next, we need to build a combined netlist. Finally the post-netlist (compare) steps must be merged.  The figure below shows how these steps can be roughly mapped from the traditional separate LVS jobs to a single combined LVS job.

Summary

What I've tried to show here is that simultaneous 3D physical verification is possible, but that with existing tools, manual merging of the data, DRC, and LVS runsets are required.  I invite any comments on what I'm suggesting here, and if anyone wants to take this beyond intellectual curiosity, by all means, post a comment or shoot me an email.

3D Integrated Circuit Physical Verification

Continuing on the 'can IC Validator do that?" theme - another question I am often asked is "What do I have to do special with DRC and LVS to make my 3D packaged die work?".  Very much like my last thread, the short answer is what you're hoping to hear - "Nothing!".  Disclaimer - don't go off and tell your manager that just yet.  There are a few nuances, but in general, your physical verification design flow won't change dramatically.  In other words, read on....

One more disclaimer: In this discussion, I will deal only with the question of verifying each die individually.  Verifying multiple chips simultaneously brings a different set of challenges.  I'll address the question of the simultaneously verifying mulitple die in a separate email.

There are really two types of multi-die packages used in the industry today that use the monicker "3D-IC".  They are generally referred to as silicon-interposer and stacked die.  In both cases, the impact on physical verification is similar.

Silicon interposer

This type of multi-die configuration generally involves a set of 'high performance' chips, which are connected together by a chip on a lower-cost semiconductor process (the interposer).  The high performance chips perform the active functions of the product, while the interposer either has no active circuitry, or simple buffering circuitry to provide the inter-chip connectivity.  The functioning component chips are distributed on top of the interposer chip in a 1-D or 2-D array.  This is the most commonly discussed 3D-IC configuration in technical publications.

Silicon Interposer

Stacked Die

While a silicon interposer arranges the functioning chips in the "X" and "Y" dimensions, a stacked die arranges them in the "Z" direction.  This results in a much smaller footprint for the resulting package, however, it comes at the cost of reduced thermal conductivity.  That means you can't put a lot of high speed function into the stacked chips.  This type of configuration is being explored primarily for increasing memory density by stacking DRAM chips, such as Micron's Hybrid Memory Cube.

Stacked Die

DRC

The primary function of DRC is to evaluate geometric relationships between mask layers to ensure they can successfully be manufactured.  With 3D-IC, additional mask layers are introduced to support the TSVs. These layers are unlike traditional interconnect layers - which sit 'above' the active devices, and are co-planar only with themselves and vias.  Therefore, many additional rules to check the interaction of the TSVs and other design layers must be included.

Additional rules pertaining to the TSVs answer the following manufacturability questions:

• What TSV sizes and pitches can result in a functioning and reliable chip? (Chan2013)
• What layer in the metal stack does the TSV connect to? (M1 in most of the public examples)
• What overlaps/or and spacings are required between other layers (ie NWELL or device layers) and the TSV?
• For the metal layer that contacts the TSV, what are the via-coverage requirements (overlaps)

All of these questions can be validated using traditional DRC techniques.

In addition to rules governing the placement of the TSVs themselves, stacking chips eliminates the traditional path of heat flow off of the chip: the substrate.  When chips are stacked, the back side is no longer a heat sink, but is abutted to another chip.  In some cases, rules that relate to thermal effects (and secondary thermal effects such as reliability) may have to be tightened up.

LVS

The function of LVS for integrated circuits is to confirm that the design intent (schematic) is correctly implemented (layout).  The interface for the design are the primary inputs and outputs (I/Os).  On a standard (non-3D) chip, these I/Os are either the exposed C4s (flip-chip connections) or the bondpads on the surface of the chip.  The LVS process compares the circuitry in the design, and its connections to the I/Os to ensure the schematic was correctly implemented.

For 3D-IC, the most significant difference from an LVS perspective is the addition of chip connections through the TSV.  That means that in addition to C4/bondpads on the surface of the chip, there are also I/O connections from the TSV on the back of the chip.  The layout extraction phase of LVS must make sure to discover I/Os in both places.  This is an incremental change to traditional LVS.  Once the I/Os are established, the comparison to the schematic is straightforward.

It is also possible to model the TSV as a device.  It is a complex parasitic connector, and modeling it properly can be critical for circuit function.  The device models are generally 2-terminal, in some cases, they also include ground coupling (Kim2011).  Extraction of 2-terminal vertical devices in LVS is well established, and does not present any additional challenges.

Summary

For both LVS and DRC, there are additional constraints placed upon the design by the TSVs that will impact designs.  These may also have minor impacts on the runtime of DRC and LVS.  In general, however, the bulk of the physical verification flow for each individual chip will not be hugely impacted.

Physical design and verification can get more interesting if one were to verify the entire system at once.  In other words - a single schematic for the entire system of chips, plus a single layout representing the entire system.  I'll address that question in my next post.

References

• Joohee Kim et al., "High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)", IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 1, No. 2, Feb 2011, p181
• Yuen Sing Chan, Hong Yu Li, Xiaowu Zhang, "Thermo-Mechanical Design Rules for the Fabrication of TSV Interposers", IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 3, No. 4, April 2013, p633
• Samsung Foundry, "3D TSV Technology & Wide IO Memory Solutions", http://www.samsung.com/us/business/oem-solutions/pdfs/Web_DAC2012_TSV_demo-ah.pdf
• Mustafa Badaroglu & Pol Marchal, "3D Integration Technology Basics and Its Impact on Design", http://www.cse.psu.edu/~yuanxie/ISCA10-WTAI/3D-Badaroglu-IMEC.pdf
• Tzu Kun Ku, "3D TSV Stacking IC Technologies, Challenges & Opportunities", http://sites.amd.com/us/Documents/TFE2011_026ITR.pdf
• Micron, "All About HMC", http://www.micron.com/products/hybrid-memory-cube/all-about-hmc
• Michael Jackson, "A Silicon Interposer-based 2.5D-IC Design Flow, Going 3D by Evolution Rather than by Revolution", https://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art3-3ddesign-flow-IssQ1-12.aspx?cmp=Insight-I1-2012-Art3