3D Integrated Circuit Physical Verification

Continuing on the 'can IC Validator do that?" theme - another question I am often asked is "What do I have to do special with DRC and LVS to make my 3D packaged die work?".  Very much like my last thread, the short answer is what you're hoping to hear - "Nothing!".  Disclaimer - don't go off and tell your manager that just yet.  There are a few nuances, but in general, your physical verification design flow won't change dramatically.  In other words, read on....

One more disclaimer: In this discussion, I will deal only with the question of verifying each die individually.  Verifying multiple chips simultaneously brings a different set of challenges.  I'll address the question of the simultaneously verifying mulitple die in a separate email.

There are really two types of multi-die packages used in the industry today that use the monicker "3D-IC".  They are generally referred to as silicon-interposer and stacked die.  In both cases, the impact on physical verification is similar.

Silicon interposer

This type of multi-die configuration generally involves a set of 'high performance' chips, which are connected together by a chip on a lower-cost semiconductor process (the interposer).  The high performance chips perform the active functions of the product, while the interposer either has no active circuitry, or simple buffering circuitry to provide the inter-chip connectivity.  The functioning component chips are distributed on top of the interposer chip in a 1-D or 2-D array.  This is the most commonly discussed 3D-IC configuration in technical publications.

Silicon Interposer

Stacked Die

While a silicon interposer arranges the functioning chips in the "X" and "Y" dimensions, a stacked die arranges them in the "Z" direction.  This results in a much smaller footprint for the resulting package, however, it comes at the cost of reduced thermal conductivity.  That means you can't put a lot of high speed function into the stacked chips.  This type of configuration is being explored primarily for increasing memory density by stacking DRAM chips, such as Micron's Hybrid Memory Cube.

Stacked Die

DRC

The primary function of DRC is to evaluate geometric relationships between mask layers to ensure they can successfully be manufactured.  With 3D-IC, additional mask layers are introduced to support the TSVs. These layers are unlike traditional interconnect layers - which sit 'above' the active devices, and are co-planar only with themselves and vias.  Therefore, many additional rules to check the interaction of the TSVs and other design layers must be included.

Additional rules pertaining to the TSVs answer the following manufacturability questions:

• What TSV sizes and pitches can result in a functioning and reliable chip? (Chan2013)
• What layer in the metal stack does the TSV connect to? (M1 in most of the public examples)
• What overlaps/or and spacings are required between other layers (ie NWELL or device layers) and the TSV?
• For the metal layer that contacts the TSV, what are the via-coverage requirements (overlaps)

All of these questions can be validated using traditional DRC techniques.

In addition to rules governing the placement of the TSVs themselves, stacking chips eliminates the traditional path of heat flow off of the chip: the substrate.  When chips are stacked, the back side is no longer a heat sink, but is abutted to another chip.  In some cases, rules that relate to thermal effects (and secondary thermal effects such as reliability) may have to be tightened up.

LVS

The function of LVS for integrated circuits is to confirm that the design intent (schematic) is correctly implemented (layout).  The interface for the design are the primary inputs and outputs (I/Os).  On a standard (non-3D) chip, these I/Os are either the exposed C4s (flip-chip connections) or the bondpads on the surface of the chip.  The LVS process compares the circuitry in the design, and its connections to the I/Os to ensure the schematic was correctly implemented.

For 3D-IC, the most significant difference from an LVS perspective is the addition of chip connections through the TSV.  That means that in addition to C4/bondpads on the surface of the chip, there are also I/O connections from the TSV on the back of the chip.  The layout extraction phase of LVS must make sure to discover I/Os in both places.  This is an incremental change to traditional LVS.  Once the I/Os are established, the comparison to the schematic is straightforward.

It is also possible to model the TSV as a device.  It is a complex parasitic connector, and modeling it properly can be critical for circuit function.  The device models are generally 2-terminal, in some cases, they also include ground coupling (Kim2011).  Extraction of 2-terminal vertical devices in LVS is well established, and does not present any additional challenges.

Summary

For both LVS and DRC, there are additional constraints placed upon the design by the TSVs that will impact designs.  These may also have minor impacts on the runtime of DRC and LVS.  In general, however, the bulk of the physical verification flow for each individual chip will not be hugely impacted.

Physical design and verification can get more interesting if one were to verify the entire system at once.  In other words - a single schematic for the entire system of chips, plus a single layout representing the entire system.  I'll address that question in my next post.

References

• Joohee Kim et al., "High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)", IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 1, No. 2, Feb 2011, p181
• Yuen Sing Chan, Hong Yu Li, Xiaowu Zhang, "Thermo-Mechanical Design Rules for the Fabrication of TSV Interposers", IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 3, No. 4, April 2013, p633
• Samsung Foundry, "3D TSV Technology & Wide IO Memory Solutions", http://www.samsung.com/us/business/oem-solutions/pdfs/Web_DAC2012_TSV_demo-ah.pdf
• Mustafa Badaroglu & Pol Marchal, "3D Integration Technology Basics and Its Impact on Design", http://www.cse.psu.edu/~yuanxie/ISCA10-WTAI/3D-Badaroglu-IMEC.pdf
• Tzu Kun Ku, "3D TSV Stacking IC Technologies, Challenges & Opportunities", http://sites.amd.com/us/Documents/TFE2011_026ITR.pdf
• Micron, "All About HMC", http://www.micron.com/products/hybrid-memory-cube/all-about-hmc
• Michael Jackson, "A Silicon Interposer-based 2.5D-IC Design Flow, Going 3D by Evolution Rather than by Revolution", https://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art3-3ddesign-flow-IssQ1-12.aspx?cmp=Insight-I1-2012-Art3

How do FinFets impact Physical Verification (DRC/LVS)?

I am often asked the question, "Does IC Validator support FinFETs?".  I won't discuss details of the Synopsys products today, but I will talk in general about what it means for a DRC/LVS tool to support FinFETs.  Many EDA tools are impacted by the use of FinFETs - most notably SPICE simulators and parasitic extraction engines.  So how is physical verification impacted?  Let's start by reviewing how a FinFET compares to a standard MOSFET.

FinFET and Planar MOSFET Layout and Model

The FinFET structure has been around for some time, but has only been introduced commercially in recent years.  Most semiconductor foundries are introducing FinFETs as they build technologies below the 20nm process node.  A FinFET offers many electrical advantages over traditional planar MOSFETs that I won't discuss here.  With a FinFET, the channel is 'raised' into a fin, with the gate wrapped around it.  From a 3-dimensional perspective, this is quite complex, but for mask manufacturing purposes, it requires a standard set of 2-D masks.

The standard device model of a FinFET is a 3-terminal device with optional bulk nodes.  The FinFET netlist topology is identical to that of the planar MOSFET.  In addition to the length and width parameters, it will include additional device properties describing FIN configurations.

FinFETs and DRC

A DRC tool's job is to look at layers of 2-D geometries and report errors due to interactions and measurements:

• on a single mask layer
• between multiple layers
• between layers in context of a complex net-connection structure (ie same-net checks, antenna checks, net-voltage checks)

If we consider this in context of a FinFET - you can see that a FinFET is built from a simple collection of 2-D masks.  While it may have many additional rules - the rules will all fit into one of the 3 categories above.  What we are finding in practice is that to effectively manufacture these devices at extremely tight pitches, the design rules for FinFET layers are much more restrictive, and in some ways, much simpler to manage as a designer than planar MOSFET rules.

FinFETs and LVS

An LVS tool's job is to extract and compare MOSFET devices (plus any other device types which are not relevant to this discussion).  At a minimum, it must extract a MOSFET with gate, source, and drain terminals.  For most modern technologies, the LVS tool must also extract at least one bulk terminal.  Standard properties extracted and compared on MOSFETs are width and length.

As you can see from the image above, the 2-D layout of a FinFET is nearly identical to a planar MOSFET.  Therefore, the task of identifying and extracting the FinFET device is trivial for an LVS tool that can extract a 4-terminal MOSFET.  Calculation of the FinFET properties requires slightly different measurement techniques than for a planar MOSFET.  Fortunately, most modern LVS tools have had features to support this for many technology nodes.

Summary

DRC and LVS tools that support recent process nodes should have no difficulty supporting the additional demands of FinFETs.  A foundry writing DRC and LVS runsets to support FinFETs will face additional complexities of adding new DRC rules, and supporting FinFET device definition/properties for LVS.  As a designer, you may experience different types of rules, and different failure modes in LVS.  However, the software itself should support FinFETs without modification.

Keep in mind that I refer here only to the impact of FinFET - there are many other features of sub-20nm technologies that will impact Physical Verification tools that I will discuss in future blog posts.

I invite any feedback and comments.

First Blog Post!

Welcome to my first blog!  I hope you’ll join me as I share news and fun information about semiconductors and electronic design automation for as long as this lasts!